Semiconductor integrated circuits are designed and fabricated by first preparing a schematic diagram or hardware description language (HDL) specification of a logical circuit in which functional elements are interconnected to perform a particular logical function. With standard cell technology, for example, the schematic diagram or HDL specification is synthesized into standard cells of a particular cell library. Each standard cell corresponds to a logical function unit, which is implemented by one or more transistors that are optimized for the cell. A series of computer-aided design tools generate a netlist of the selected cells and the interconnections between the cells. The netlist is used by a floor-planner or placement tool to place the selected cells at particular locations in an integrated circuit layout pattern. The interconnections between the cells are then routed along predetermined routing layers. Once the selected cells have been placed and routed, the netlist, the cell layout definitions, the placement data and the routing data together form an integrated circuit layout definition, which is used to fabricate the integrated circuit.
In some integrated circuit technologies, such as structured application specific integrated circuits, an initial floorplan is generated in which certain “floor-planned” objects are pre-placed in the layout pattern. A design can then be mapped to the floorplan. For example, with LSI Logic Corporation's RapidChip™ program, the designer is provided with a pre-built slice containing power and ground nets as well as aggregations of proven intellectual property. The slice can also include an input-output ring, as well as other physical elements such as hard macros, diffused memory, and standard cells. These pre-defined objects form part of an initial floorplan, which can also include placement of soft blockage locations and layer-specific routing obstructions.
Using the initial floorplan input, the schematic diagram or HDL specification is physically synthesized, placed relative to the floorplan, and routed. Based on the placement and routing information, a timing analysis tool identifies any timing problems and optimizes the physical synthesis, placement and/or routing in order to improve any critical timing paths.
However, due to the complexity of a typical design and layout pattern, some timing problems may be corrected with routine optimization. The causes of some timing problems and their solutions can be very difficult to identify. This is particularly true for timing problems caused by faulty floor-planning.
Floor-planning is difficult, and there seems to be a general consensus that logic designers are not very good at floor-planning. But at the same time, industry movement toward the use of structured ASICs has shifted the burden of floor-planning to the logic designer. Since a typical logic designer does not have the expertise and experience to produce a good floorplan, the initial floorplan developed by a logic designer can often lead to design closure problems. Design closure problems can include timing closure, design rule check (DRC) violations, and other physical issues that traditionally are difficult to trace back to a faulty floorplan.
In order to identify problems in the floorplan that are causing timing problems during timing analysis, designers potentially have to analyze hundred to tens of thousands of timing paths. These paths not only include paths having timing violations, but also paths that just barely satisfy the timing criteria. These timing paths need to be evaluated within the context of the floorplan in order to determine if the floorplan is the root cause of the problem.
Changing the floorplan to provide a different starting point for the design system (including physical synthesis or placement tools) is another strategy that has been employed. Typically, this is done by individuals who are floor-planning experts. A different starting point can also be accomplished by randomly changing the floorplan and re-evaluating. In either case, the best result is chosen.
Having a floor-planning expert available to floorplan a design has several problems. The first is that floor-planning expertise is a rare skill that is hard to obtain. The second is that it can be very expensive to make use this kind of expertise if it can be found. Also, randomly changing the floorplan to try to discover a floorplan that produces a good quality result can be very time consuming, and it is not guaranteed to generate a solution. Further, there could be too many floorplan possibilities to try them all. Such efforts consume a large amount of design resources.
Trying to analyze hundreds or thousands of timing paths and look for problems caused by the floorplan is a complex task that is iterative and very time consuming. This skill is typically beyond what a logic designer has developed. This leads to a very steep learning curve that can extend the design cycle significantly. Lack of up front consideration and resolution of floorplan problems can have a very significant impact on the architecture and structure of the design. If floorplan changes are pushed out to a later date due to lack of experience, then it is that much harder to make fundamental changes to the design to facilitate design closure due to schedule pressures. At the same time, changes made to a floorplan to achieve design closure can ripple back through all of the design verification processes.
Improved methods of identifying floorplan problems are therefore desired.